1. Field of the Invention
The present invention relates to an LCD driving circuit, and more particularly, to a gate driver capable of repairing defective stages, and a repairing method thereof.
2. Discussion of the Related Art
A Liquid Crystal Display (LCD) device displays images by controlling light transmittance of liquid crystal using electric fields. The LCD device includes a liquid crystal display panel in which pixels are arranged in a matrix format and driving circuits for driving the LCD panel.
The LCD panel is configured such that a plurality of gate lines and a plurality of data lines orthogonally cross each other to define pixel areas within the crossings of the gate lines and the data lines. The LCD panel includes pixel electrodes and common electrodes for applying electric fields to the pixel areas.
Respective pixel electrodes are connected to the data lines via the sources and drains of thin film transistors (TFTs) employed as switching elements in each pixel. The TFTs are turned on by scan pulses applied to the gates via the gate lines to allow voltages corresponding to the data signals of the data lines to be charged to the pixel areas.
The driving circuits include a gate driver for driving the gate lines; a data driver for driving data lines; a timing controller for providing control signals for controlling the gate driver and data driver; and a power supply unit for providing various driving voltages used in the LCD device.
The timing controller serves to control driving timing of the gate driver and the data driver and to provide the pixel data to the data driver. The power supply unit serves to boost or diminish an input voltage to generate a common voltage VCOM and driving voltages for a gate high voltage signal VGH, a gate low voltage signal VGL and other voltages. In addition, the gate driver sequentially provides the scan pulses to the gate lines to sequentially drive liquid crystal cells of an LCD panel line by line. The data driver provides pixel voltage signals to each data line each time a scan pulse is provided to one of the gate lines. The light transmittance of the LCD panel is controlled by electric fields that are applied to the pixel electrodes and the common electrodes of LC cells according to the pixel voltage signals to display images on the LCD panel.
The gate driver includes a shift register to sequentially supply the above-described scan pulses.
A driving circuit of the related art will be described in detail with reference to FIG. 1.
FIG. 1 illustrates a shift register of the related art.
The shift register of the related art includes a plurality of stages ST101˜ST10n+1 which are dependently connected to each other. The stages ST101˜ST10n not including a dummy stage ST10n+1 sequentially output scan pulses to the gate lines included in the display unit.
Each of the stages ST101˜ST10n+1 is enabled as each stage receives a scan pulse outputted from the immediately preceding stage and disabled as each stage receives a scan pulse outputted from the immediately following stage.
For example, the 2nd stage ST102 is enabled as it inputs a scan pulse from the 1st stage ST101 and disabled as it inputs a scan pulse from the 3rd stage ST103.
To this end, each of the stages ST101˜ST10n has three output lines 141a, 141b, and 141c, as shown in 2nd stage ST102, for example.
The first output line 141a is electrically connected between a corresponding stage and a corresponding gate line. The second output line 141b is electrically connected between the first output line 141a and the following stage thereof. The third output line 141c is electrically connected between the first output line 141a and the preceding stage thereof.
If a defect occurs in one of the stages ST101˜STn+1 such that the defective stage cannot be operated, none of the stages following the defective stage will be able to output a scan pulse.
For example, as shown in FIG. 1, when the 3rd stage ST103 is inoperable due to a defect, it does not output a scan pulse.
In a normal state, the 4th stage ST104 immediately following the 3rd stage ST103 is enabled as it receives a scan pulse outputted from the 3rd stage ST103. However, because the 3rd stage ST103 has been rendered inoperable due to a malfunction as described above, the 4th stage ST104 is not enabled to output a scan pulse.
Similarly, in the normal state, the 5th stage ST105 immediately following the 4th stage ST104 is enabled as it inputs a scan pulse outputted from the 4th stage ST104. However, since the 4th stage ST104 does not output a scan pulse because of the failure of the 3rd stage, the 5th stage ST105 cannot be enabled.
The remaining stages, from the 6th stage to the nth stage ST10n will be similarly unable output scan pulses.
Therefore, the third to nth gate lines, which are connected to the 3rd stage ST103 to the nth stage ST10n, cannot be operated due to the defect in the 3rd stage. Accordingly, pixel cells connected to the 3rd to nth gate lines cannot display images.